The PDP-11 series of computers from Digital Equipment Corporation were popular 16-bit mini-computers from 1970 through the early 1980s. The first model was the PDP-11/20, released in 1970. The successor to the PDP-11 line was the VAX series.
DEC sold its PDP-11 hardware and software rights to Mentec in 1994.
DEC wrote a PDP-10 program to simulate any computer based on its ISP (Instruction Set Processor) description. Using this program, DEC performed benchmark comparisons on numerous potential computer designs. The goal was to optimize total system performance, ease of writing code, efficiency of that code, and other considerations. The result was the PDP-11 line.
Data size = 16 bits
Address size = 18-24 bits
16-bit Registers: R0, R1, R2, R3, R4, R5, R6 (SP), R7 (PC), PSW
The 11/45, 11/70, and Micro/J-11 had two sets of registers R0-R5. These models, along with the 11/44 supported multiple privilege levels: Kernel, User, and (except for the 11/44) Supervisor.
The instruction set varied somewhat between the different models. There was a basic instruction set possessed by all models. In addition, some models supported additional instructions, and/or FIS (floating-point 32-bit and 64-bit), and/or other extensions. The EIS (Extended Instruction Set) supported integer math. The CIS (Commercial Instruction Set) included 10 different forms of string manipulation instructions. The Micro/J-11 supported all of the possible PDP-11 instructions, except for those unique to the PDP-11/60, and the PDP-11/34 (MTPS and MFPS). Even among the basic instruction set, there were some slight differences in behavior of some instructions on different models. However, with care, software was compatible across the entire line.
All I/O was through memory-mapped devices as the CPUs did not support I/O instructions.
Basic instruction set: ADC, ADCB, ADD, ASL, ASLB, ASR, ASRB, BCC, BCS, BIC, BICB, BIS, BISB, BIT, BITB, BEQ, BGE, BGT, BHI, BHIS, BLE, BLO, BLOS, BLT, BMI, BNE, BPL, BPT, BR, BVC, BVS, CCC, CLC, CLN, CLR, CLRB, CLV, CLZ, CMP, CMPB, COM, COMB, DEC, DECB, EMT, HALT, INC, INCB, IOT, JMP, JSR, MOV, MOVB, NEG, NEGB, RESET, ROL, ROLB, ROR, RORB, RTI, RTS, RTT, SBC, SBCB, SCC, SEC, SEN, SEV, SEZ, SUB, SWAB, SXT, TST, TRAP, TSTB, WAIT.
Extended Instruction Set (EIS): ASH, ASHC, DIV, MUL, XOR.
Commercial Instruction Set (CIS): ADDN, ADDNI, ADDP, ADDPI, ASHN, ASHNI, ASHP, ASHPI, CMPC, CMPCI, CMPN, CMPNI, CMPP, CMPPI, CVTLN, CVTLNI, CVTLP, CVTLPI, CVTNL, CVTNLI, CVTNP, CVTNPI, CVTPL, CVTPLI, CVTPN, CVTPNI, DIVP, DIVPI, L2DR, L3DR, LOCC, LOCCI, MATC, MATCI, MOVC, MOVCI, MOVRC, MOVRCI, MOVTC, MOVTCI, MULP, MULPI, SCANC, SCANCI, SKPC, SKPCI, SPANC, SPANCI, SUBN, SUBNI, SUBP, SUBPI.
Floating-point Instruction Set (FIS): ABSD, ABSF, ADDD, ADDF, CFCC, CLRD, CLRF, CMPD, CMPF, DIVD, DIVF, LCDF, LDCFD, LDCID, LDCIF, LDCLD, LDCLF, LDD, LDEXP, LDF, LDFPS, MODD, MODF, MULD, MULF, NEGD, NEGF, SETD, SETF, SETI, SETL, STCDF, STCDF, STCDI, STCDL, STCFI, STCFL, STD, STEXP, STF, STFPS, STST, SUBD, SUBF, TSTD, TSTF.
Other instructions (present on some models): CSM, MARK, MFPS, MFPI, MFPD, MFPT, MTPS, RTT, SOB, SPL, SXT.
The 16-bit architecture meant that a program had to fit within 64 Kb of memory for both data and instructions, although some models supported separate Instruction and Data space, allowing 64 Kb for each, per program, if the operating system allowed it.
Each PDP-11 model had one of three buses: LSI-11, QBUS, and UNIBUS. Certain models also had MASSBUS buses in addition to the UNIBUS.
The PDP-11/05 and PDP-11/10 had a KD11-B CPU and were the low-end UNIBUS systems.
The PDP-11/20 (and PDP-11/15) had a KA11 CPU and was the first PDP-11 that DEC released, in 1970. The PDP-11/r20 was a ruggedized version in a rack-mount form. Both models used core memory and the UNIBUS. They were available as desktop or rack-mount systems.
The PDP-11/45 had a KB11 or KB11-A CPU and used the UNIBUS and had an integral FP11-C FPP. It could be configured with Core, MOS, or Bipolar memory. The PDP-11/55 was identical to a PDP-11/45 with Bipolar memory. The CPUs supported EIS and dual Instruction/Data space. In most respects, the 11/45 CPU was equivalent to the 11/70, but did not support the memory size. Third-party hardware (and software patches) provided the CPU with additional memory capacity.
The PDP-11/60 had a KD11-K CPU and optional FP11-E FPP. It had MOS memory and a writable control store.
The PDP-11/70 had a KB11-B or KB11-C CPU and was the top-end minicomputer of the PDP-11 line. It was a rack-mount system. The CPU cabinet weighed 500 lbs. It used the UNIBUS, MASSBUS, and MOS memory. The CPU supported EIS and dual Instruction/Data space.
The Micro/T-11, Micro/J-11, and Micro/F-11 were PDP-11 CPUs implemented in a microprocessor.
The PDP-11/53 and PDP-11/73 both had Micro/J-11 CPUs.
The PDP-11/93 and PDP-11/94 were the highest-performance PDP-11s commercially produced. Both systems used the Micro/J-11 processor.
The PDP-11/74 was a multiprocessor system consisting of 4 PDP-11/70 CPUs. The development of the system was terminated before it was commercially released.
The following is a comparison of the systems in the PDP-11 series, performance is the maximum performance (with bipolar RAM) relative to a standardized rating of 1:
|System_Model||Performance||Max memory||System Bus||Aggregate I/O|
|PDP-11/34||.13||248 Kb (4 Mb)||UNIBUS||2.5|
|PDP-11/34c||.27||248 Kb (4 Mb)||UNIBUS||2.5|
|PDP-11/45||.6||248 Kb (4 Mb)||UNIBUS, MASSBUS||5.8|
|PDP-11/70||.6||4 Mb||UNIBUS, MASSBUS||5.8|
DEC wrote a number of software products for the PDP-11 line. The operating systems included RSX-11, RT-11, MUMPS-11, IAS, and RSTS. User and development applications were also provided by DEC and third party companies.
- SimH software (freeware)
- CEF32 (freeware)
- Ersatz-11 software emulator (both freeware/hobbyist and commercial versions)
- CHARON-11 software emulators
- StrobeData's PDP-11-on-a-board for your PC
- WinSoft Cobra-11 hardware emulator for the PDP-11
- PDP11/20/15/r20 Processor Handbook, DEC, 1971
- PDP 11/45 Processor Handbook, DEC, 1973
- PDP 11/34 Processor Handbook, DEC, 1976
- PDP 11/70 Processor Handbook, DEC, 1976
- PDP 11/60 Processor Handbook, DEC, 1977
- PDP11/04/34/45/55/60 Processor Handbook, DEC, 1978
- PDP11/04/34a/44/60/70 Processor Handbook, DEC, 1979
- PDP-11 Micro/PDP-11 Handbook, DEC, 1983
- PDP-11 Relative Performance
- The PDP-11