Central processing unit - Revision history

Eac: Slight correction

2020-07-24T23:32:47Z

Slight correction

Eac: Removed duplicate information

2020-02-15T08:16:55Z

Removed duplicate information

Eac: /* Operation */

2020-02-15T08:15:51Z

Operation

Eac: Expanded article

2020-02-13T06:44:09Z

Expanded article

DavidB4: cleanup

2019-06-01T03:32:53Z

cleanup

DavidB4: reordered, trimmed categories

2018-01-12T03:38:53Z

reordered, trimmed categories

1990'sguy: Duplicate.

2018-01-12T03:05:56Z

Duplicate.

1990'sguy: Clean up.

2018-01-12T03:05:25Z

Clean up.

DavidB4: /* Prescient Quotes on Police State Hardware Surveillance */ -TAR

2018-01-12T03:02:27Z

Prescient Quotes on Police State Hardware Surveillance: -TAR

DavidB4-bot: clean up

2016-06-23T14:59:11Z

clean up

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 == Operation ==
-The basic operation of a CPU is the "Fetch, Decode, Execute" cycle.<ref>[http://www.it.jcu.edu.au/Subjects/cp1300/resources/lectnotes/system/fde.html Fetch-Decode-Execute Cycle]</ref>  The ''instruction fetcher'' fetches instructions from memory.  The ''control logic'' decodes and executes the instruction.  The [[ALU]] is used to perform arithmetic and logical operations such as adding a value in memory to a value in a register and storing the result in another register.  On some CPUs, some instructions may require additional fetches from memory (e.g., to get or store operands).  A program in memory is executed sequentially, with each instruction stored in a different memory location.  The instruction pointer (IP) register keeps tracks of the current program position, and is updated (usually incremented) after each CPU cycle.
+The basic operation of a CPU is the "Fetch, Decode, Execute" cycle.<ref>[http://www.it.jcu.edu.au/Subjects/cp1300/resources/lectnotes/system/fde.html Fetch-Decode-Execute Cycle]</ref>  The ''instruction fetcher'' fetches instructions from memory.  The ''control logic'' decodes and executes the instruction.  The [[ALU]] is used to perform arithmetic and logical operations such as adding a value in memory to a value in a register and storing the result in another register.  On some CPUs, some instructions may require additional fetches from memory (e.g., to get or store operands).  A program in memory is executed sequentially, with each instruction stored in a different memory location.  The instruction pointer (IP) register keeps tracks of the current program position, and is updated (usually incremented) after each instruction is executed.
 == Architecture ==

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 ===Instruction Set===
-The instruction set of a given CPU model defines the basic operations that can be performed by the CPU.  These operations tend to be simple, such as adding two numbers, outputting a character, or moving data between registers.  In a given line of processors, the instruction sets are compatible, although as the newer models are released, they usually had additional instructions added.  Thus, newer processors were backwards compatible (meaning they could run the same programs as older processors), but older processors did not recognize the new instructions added to later models.  Between processor lines, there is no compatibility.  The instructions are stored in memory as "machine code" which are bit patterns that represent certain instructions.  These bit patterns represent entirely different operations on different processor lines, which means that a program written for one CPU will not run on a different CPU line.  Rather than programming in machine code, assemblers are used to convert from mnemonics to machine codes.  The mnemonics tend to be three or four character abbreviations that indicate the operation.  For instance, MVI (Move immediate), JP (Jump if positive), or HLT (halt).
+The instruction set of a given CPU model defines the basic operations that can be performed by the CPU.  These operations tend to be simple, such as adding two numbers, outputting a character, or moving data between registers.  In a given line of processors, the instruction sets are compatible, although as the newer models are released, they usually had additional instructions added.  Thus, newer processors were backwards compatible (meaning they could run the same programs as older processors), but older processors did not recognize the new instructions added to later models.  Between processor lines, there is no compatibility.  The instructions are stored in memory as "machine code" which are bit patterns that represent certain instructions.  These bit patterns represent entirely different operations on different processor lines, which means that a program written for one CPU will not run on a different CPU line.
 There are two aspects to an instruction set.

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 == Operation ==
-The basic operation of a CPU is the "Fetch, Decode, Execute" cycle.<ref>[http://www.it.jcu.edu.au/Subjects/cp1300/resources/lectnotes/system/fde.html Fetch-Decode-Execute Cycle]</ref>  The ''instruction fetcher'' fetches instructions from memory.  The ''control logic'' decodes and executes the instruction.  The ALU is used to perform arithmetic and logical operations such as adding a value in memory to a value in a register and storing the result in another register.  On some CPUs, some instructions may require additional fetches from memory (e.g., to get or store operands).  A program in memory is executed sequentially, with each instruction stored in a different memory location.  The instruction pointer (IP) register keeps tracks of the current program position, and is updated (usually incremented) after each CPU cycle.
+The basic operation of a CPU is the "Fetch, Decode, Execute" cycle.<ref>[http://www.it.jcu.edu.au/Subjects/cp1300/resources/lectnotes/system/fde.html Fetch-Decode-Execute Cycle]</ref>  The ''instruction fetcher'' fetches instructions from memory.  The ''control logic'' decodes and executes the instruction.  The [[ALU]] is used to perform arithmetic and logical operations such as adding a value in memory to a value in a register and storing the result in another register.  On some CPUs, some instructions may require additional fetches from memory (e.g., to get or store operands).  A program in memory is executed sequentially, with each instruction stored in a different memory location.  The instruction pointer (IP) register keeps tracks of the current program position, and is updated (usually incremented) after each CPU cycle.
 == Architecture ==

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 == Operation ==
 The basic operation of a CPU is the "Fetch, Decode, Execute" cycle.<ref>[http://www.it.jcu.edu.au/Subjects/cp1300/resources/lectnotes/system/fde.html Fetch-Decode-Execute Cycle]</ref>  The ''instruction fetcher'' fetches instructions from memory.  The ''control logic'' decodes and executes the instruction.  The ALU is used to perform arithmetic and logical operations such as adding a value in memory to a value in a register and storing the result in another register.  On some CPUs, some instructions may require additional fetches from memory (e.g., to get or store operands).  A program in memory is executed sequentially, with each instruction stored in a different memory location.  The instruction pointer (IP) register keeps tracks of the current program position, and is updated (usually incremented) after each CPU cycle.
 ==See also==

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 ==External links==
 *[http://computer.howstuffworks.com/microprocessor.htm How Microprocessors Work]
 * https://charlescarrollsociety.com/2013/06/10/prism-yes-they-can
 * https://charlescarrollsociety.com/2013/05/06/memo-to-the-police-state-progressives-please-let-his-people-go
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 * https://charlescarrollsociety.com/2014/02/12/amrd-t-a-i-l-s-plastic-gloves-for-your-computer-american-redoubt - [[Tails operating system]]
 * https://charlescarrollsociety.com/2014/01/29/amrd-introducing-the-tor-browser-bundle/ - [[Tor browser]]
 [[Category:American Inventions]]

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 * [[IBM]], [[HP]], [[Dell]] and [[Microsoft]] [[Windows]]
 * [[Mobile device]]s: [[Smartphone]]s and [[tablet computer|tablets]]
 ==External links==
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 * http://www.nocards.org - [[Coalition Against Unsolicited Commercial Email]]<ref>"CAUCE is an all volunteer, entirely web-based organization, created by Netizens to advocate for a legislative solution to the problem of UCE (spam). CAUCE began as a discussion group called SPAM-LAW, formed of members who felt that legislation was necessary to stop spam from choking the life out of the Internet. In 1997 CAUCE proposed an amendment to the Federal statute which outlaws junk "faxes" (47 USC 227) to also prohibit junk e-mail, and since then has remained a pre-eminent voice in the anti-spam community. Email: comments@cauce.org. President: Edward Cherlin."</ref>
 [[Category:American Inventions]]
 [[Category:Information Technology]]
 [[Category:Computer Science]]
 [[Category:Electrical Engineering]]

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 A microprocessor is '''any''' processor implemented on a single integrated circuit, however most microprocessors are CPUs. The largest producer of microprocessors used in general-purpose computers is [[Intel]].
 == Operation ==
 The basic operation of a CPU is the "Fetch, Decode, Execute" cycle.<ref>[http://www.it.jcu.edu.au/Subjects/cp1300/resources/lectnotes/system/fde.html Fetch-Decode-Execute Cycle]</ref>  The ''instruction fetcher'' fetches instructions from memory.  The ''control logic'' decodes and executes the instruction.  The ALU is used to perform arithmetic and logical operations such as adding a value in memory to a value in a register and storing the result in another register.  On some CPUs, some instructions may require additional fetches from memory (e.g., to get or store operands).  A program in memory is executed sequentially, with each instruction stored in a different memory location.  The instruction pointer (IP) register keeps tracks of the current program position, and is updated (usually incremented) after each CPU cycle.
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 * [http://epic.org/privacy/privacy_resources_faq.html Online Guide to Privacy Resources]<ref>"EPIC was established in 1994 to focus public attention on emerging privacy issues relating to the National Information Infrastructure, such as the Clipper Chip, the Digital Telephony proposal, medical records privacy and the sale of consumer data. EPIC conducts litigation, sponsors conferences, produces reports, publishes the EPIC Alert and leads campaigns on privacy issues. For more information email: epic-info@epic.org, or contact EPIC, 1718 Connecticut Avenue, NW, Suite 200, Washington, DC 20009. Tel: (202) 483-1140. Executive Director: Marc Rotenberg."</ref>
 * http://www.nocards.org - [[Coalition Against Unsolicited Commercial Email]]<ref>"CAUCE is an all volunteer, entirely web-based organization, created by Netizens to advocate for a legislative solution to the problem of UCE (spam). CAUCE began as a discussion group called SPAM-LAW, formed of members who felt that legislation was necessary to stop spam from choking the life out of the Internet. In 1997 CAUCE proposed an amendment to the Federal statute which outlaws junk "faxes" (47 USC 227) to also prohibit junk e-mail, and since then has remained a pre-eminent voice in the anti-spam community. Email: comments@cauce.org. President: Edward Cherlin."</ref>
 ==References==
 {{reflist|2}}
 [[Category:American Inventions]]
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 [[Category:Information Technology]]
 [[Category:Computer Science]]
 [[Category:Computers]]
 [[Category:Electrical Engineering]]