Difference between revisions of "Central processing unit"

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A microprocessor is '''any''' processor implemented on a single integrated circuit, however most microprocessors are CPUs. The largest producer of microprocessors used in general-purpose computers is [[Intel]].
 
A microprocessor is '''any''' processor implemented on a single integrated circuit, however most microprocessors are CPUs. The largest producer of microprocessors used in general-purpose computers is [[Intel]].
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== Operation ==
 
== Operation ==
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The basic operation of a CPU is the "Fetch, Decode, Execute" cycle.<ref>[http://www.it.jcu.edu.au/Subjects/cp1300/resources/lectnotes/system/fde.html Fetch-Decode-Execute Cycle]</ref>  The ''instruction fetcher'' fetches instructions from memory.  The ''control logic'' decodes and executes the instruction.  The ALU is used to perform arithmetic and logical operations such as adding a value in memory to a value in a register and storing the result in another register.  On some CPUs, some instructions may require additional fetches from memory (e.g., to get or store operands).  A program in memory is executed sequentially, with each instruction stored in a different memory location.  The instruction pointer (IP) register keeps tracks of the current program position, and is updated (usually incremented) after each CPU cycle.
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The basic operation of a CPU is the "Fetch, Decode, Execute" cycle.<ref>[http://www.it.jcu.edu.au/Subjects/cp1300/resources/lectnotes/system/fde.html Fetch-Decode-Execute Cycle]</ref>  The ''instruction fetcher'' fetches instructions from memory.  The ''control logic'' decodes and executes the instruction.  The [[ALU]] is used to perform arithmetic and logical operations such as adding a value in memory to a value in a register and storing the result in another register.  On some CPUs, some instructions may require additional fetches from memory (e.g., to get or store operands).  A program in memory is executed sequentially, with each instruction stored in a different memory location.  The instruction pointer (IP) register keeps tracks of the current program position, and is updated (usually incremented) after each instruction is executed.
 +
 
 +
== Architecture ==
 +
A CPU's architecture distinguishes it from other CPUs.  There are many aspects of CPU architecture.
 +
 
 +
===Data size===
 +
CPUs are defined by the number of bits that can be handled in a single operation.  For instance, a 16-bit CPU handles 2 bytes of data with most of its operations.  The amount of data that can be transferred to and from memory is this number of bits, which determines the width of memory required for a given CPU.  Most CPUs on the market today are 64-bit CPUs.  Operations can be performed on larger or smaller numbers of bits, but such operations tend to run more slowly because the CPU is optimized for it's native data size.
 +
 
 +
===Registers===
 +
Register sets are essentially a small amount of memory within the CPU, divided into a discrete number of registers.  There are general-purpose registers that can be used by programs and special-purpose registers that are restricted to certain functions.  General purpose registers are the native data size of the CPU.  Thus a 32-bit CPU will have 32-bit wide general-purpose registers.  Special-purpose registers are used to store flags indicating the result of arithmetic or logical operations, index into memory, and so forth.  Typical registers used for indexing into memory were the Instruction Pointer (IP) - sometimes called the Program Counter (PC) - and the Stack Pointer (SP).  Such registers which contain memory addresses tend to be twice the size of the CPU's data size.  Thus, the IP on an 8-bit CPU was 16-bits, and the IP on a 16-bit CPU was 32-bits.
 +
 
 +
===Instruction Set===
 +
The instruction set of a given CPU model defines the basic operations that can be performed by the CPU.  These operations tend to be simple, such as adding two numbers, outputting a character, or moving data between registers.  In a given line of processors, the instruction sets are compatible, although as the newer models are released, they usually had additional instructions added.  Thus, newer processors were backwards compatible (meaning they could run the same programs as older processors), but older processors did not recognize the new instructions added to later models.  Between processor lines, there is no compatibility.  The instructions are stored in memory as "machine code" which are bit patterns that represent certain instructions.  These bit patterns represent entirely different operations on different processor lines, which means that a program written for one CPU will not run on a different CPU line.
 +
 
 +
There are two aspects to an instruction set.
 +
* Orthogonality: An instruction set is considered "orthogonal" if the instructions work with all general-purpose registers.  Instruction sets which limit certain instructions to certain registers are not considered orthogonal.  In reality, instruction sets fall somewhere along a spectrum between complete orthogonality and non-orthogonality.  The [[PDP-11]] has an example of an orthogonal instruction set.
 +
* RISC/CISC:  Reduced Instruction Set Computers (RISC) have fewer instructions than Complex Instruction Set Computers (CISC), which requires more instructions to complete the same task than on CISC processors.  The advantage to RISC instruction sets is that they can be implemented with fewer transistors, which allows faster instruction execution in theory.  In practice, the clock rate is the same on RISC and CISC CPUs.  However, more cores can be fit into a given semiconductor space with a RISC architecture. ARM processors are examples of RISC CPUs.  Intel iAPX processors are examples of CISC CPUs.
  
 
==See also==
 
==See also==
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* [[IBM]], [[HP]], [[Dell]] and [[Microsoft]] [[Windows]]
 
* [[IBM]], [[HP]], [[Dell]] and [[Microsoft]] [[Windows]]
 
* [[Mobile device]]s: [[Smartphone]]s and [[tablet computer|tablets]]
 
* [[Mobile device]]s: [[Smartphone]]s and [[tablet computer|tablets]]
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==References==
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{{reflist|2}}
  
 
==External links==
 
==External links==
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*[http://computer.howstuffworks.com/microprocessor.htm How Microprocessors Work]
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* https://prism-break.org/en
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* https://www.eff.org - "Leading the fight against the [[NSA]]'s illegal [[mass surveillance]] program"
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* https://www.eff.org/secure-messaging-scorecard
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* http://justdelete.me
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* http://lifehacker.com/just-delete-me-is-a-massive-list-of-links-to-close-all-1245040101
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* [http://epic.org/privacy/privacy_resources_faq.html Online Guide to Privacy Resources]
 +
* http://www.nocards.org
 
* https://charlescarrollsociety.com/2013/06/10/prism-yes-they-can
 
* https://charlescarrollsociety.com/2013/06/10/prism-yes-they-can
 
* https://charlescarrollsociety.com/2013/05/06/memo-to-the-police-state-progressives-please-let-his-people-go
 
* https://charlescarrollsociety.com/2013/05/06/memo-to-the-police-state-progressives-please-let-his-people-go
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* https://charlescarrollsociety.com/2014/02/12/amrd-t-a-i-l-s-plastic-gloves-for-your-computer-american-redoubt - [[Tails operating system]]
 
* https://charlescarrollsociety.com/2014/02/12/amrd-t-a-i-l-s-plastic-gloves-for-your-computer-american-redoubt - [[Tails operating system]]
 
* https://charlescarrollsociety.com/2014/01/29/amrd-introducing-the-tor-browser-bundle/ - [[Tor browser]]
 
* https://charlescarrollsociety.com/2014/01/29/amrd-introducing-the-tor-browser-bundle/ - [[Tor browser]]
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* https://prism-break.org/en - "Opt out of global data surveillance programs like [[PRISM]], [[XKeyscore]] and [[Tempora]]."<ref>"Help make [[mass surveillance]] of entire populations uneconomical. We all have a [[right to privacy]], which you can exercise today by [[encrypt]]ing your communications and ending your reliance on proprietary services."</ref>
 
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* https://www.eff.org - "Leading the fight against the [[NSA]]'s illegal [[mass surveillance]] program"<ref>"Organization formed in 1990 to maintain and enhance intellectual freedom, privacy, and other values of civil liberties and democracy in networked communications. Publishes newsletters, Internet Guidebooks and other documents, provides mailing lists and other online forums, and hosts a large electronic document archive. Contact: info@eff.org. 454 Shotwell Street, San Francisco, CA 94110-1914. Tel: (415) 436-9333. Fax: (415) 436-9993. Executive Director: Sheryl Steele."</ref>
 
−
* https://www.eff.org/secure-messaging-scorecard
 
−
* http://justdelete.me
 
−
* http://lifehacker.com/just-delete-me-is-a-massive-list-of-links-to-close-all-1245040101
 
−
* [http://epic.org/privacy/privacy_resources_faq.html Online Guide to Privacy Resources]<ref>"EPIC was established in 1994 to focus public attention on emerging privacy issues relating to the National Information Infrastructure, such as the Clipper Chip, the Digital Telephony proposal, medical records privacy and the sale of consumer data. EPIC conducts litigation, sponsors conferences, produces reports, publishes the EPIC Alert and leads campaigns on privacy issues. For more information email: epic-info@epic.org, or contact EPIC, 1718 Connecticut Avenue, NW, Suite 200, Washington, DC 20009. Tel: (202) 483-1140. Executive Director: Marc Rotenberg."</ref>
 
−
* http://www.nocards.org - [[Coalition Against Unsolicited Commercial Email]]<ref>"CAUCE is an all volunteer, entirely web-based organization, created by Netizens to advocate for a legislative solution to the problem of UCE (spam). CAUCE began as a discussion group called SPAM-LAW, formed of members who felt that legislation was necessary to stop spam from choking the life out of the Internet. In 1997 CAUCE proposed an amendment to the Federal statute which outlaws junk "faxes" (47 USC 227) to also prohibit junk e-mail, and since then has remained a pre-eminent voice in the anti-spam community. Email: comments@cauce.org. President: Edward Cherlin."</ref>
 
−
 
−
 
−
==References==
 
−
{{reflist|2}}
 
  
 
[[Category:American Inventions]]
 
[[Category:American Inventions]]
−
[[Category:Cryptography]]
 
−
[[Category:Technology]]
 
 
[[Category:Information Technology]]
 
[[Category:Information Technology]]
 
[[Category:Computer Science]]
 
[[Category:Computer Science]]
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−
 
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== External links ==
 
−
*[http://computer.howstuffworks.com/microprocessor.htm How Microprocessors Work]
 
−
 
−
[[Category:Computers]]
 
 
[[Category:Electrical Engineering]]
 
[[Category:Electrical Engineering]]

Latest revision as of 23:32, July 24, 2020

Block Diagram of a simple CPU

A Central Processing Unit (CPU) is the main control mechanism of a computer, containing control logic, registers, and arithmetic logic unit (ALU) as well as a memory interface. Some CPUs implement additional functionality, but often other capabilities are provided through peripheral processors that handle such things as input/output (I/O), floating-point arithmetic, and vector processing. All computers contain at least one CPU, but some contemporary computers contain over 1,000.

The purpose of a CPU is to execute programs. Programs are a series of numeric values, where each value indicates a specific operation. Each value is referred to as an instruction, and has a corresponding mnemonic for programming convenience. These values are known as machine code. All of the instructions that can be executed by a CPU are collectively known as the CPU's instruction set. Different CPU models usually implement completely different instruction sets, so that programs written for one CPU will not execute on a different one. Writing programs in machine code is difficult, so programs called assemblers were written to translate mnemonics into machine code, thus increasing the speed of writing, and the reliability of, programs. Since the 1960s, most programs have been written using a Programming Language, which are even easier to use than an assembler.

A microprocessor is any processor implemented on a single integrated circuit, however most microprocessors are CPUs. The largest producer of microprocessors used in general-purpose computers is Intel.

Operation

The basic operation of a CPU is the "Fetch, Decode, Execute" cycle.[1] The instruction fetcher fetches instructions from memory. The control logic decodes and executes the instruction. The ALU is used to perform arithmetic and logical operations such as adding a value in memory to a value in a register and storing the result in another register. On some CPUs, some instructions may require additional fetches from memory (e.g., to get or store operands). A program in memory is executed sequentially, with each instruction stored in a different memory location. The instruction pointer (IP) register keeps tracks of the current program position, and is updated (usually incremented) after each instruction is executed.

Architecture

A CPU's architecture distinguishes it from other CPUs. There are many aspects of CPU architecture.

Data size

CPUs are defined by the number of bits that can be handled in a single operation. For instance, a 16-bit CPU handles 2 bytes of data with most of its operations. The amount of data that can be transferred to and from memory is this number of bits, which determines the width of memory required for a given CPU. Most CPUs on the market today are 64-bit CPUs. Operations can be performed on larger or smaller numbers of bits, but such operations tend to run more slowly because the CPU is optimized for it's native data size.

Registers

Register sets are essentially a small amount of memory within the CPU, divided into a discrete number of registers. There are general-purpose registers that can be used by programs and special-purpose registers that are restricted to certain functions. General purpose registers are the native data size of the CPU. Thus a 32-bit CPU will have 32-bit wide general-purpose registers. Special-purpose registers are used to store flags indicating the result of arithmetic or logical operations, index into memory, and so forth. Typical registers used for indexing into memory were the Instruction Pointer (IP) - sometimes called the Program Counter (PC) - and the Stack Pointer (SP). Such registers which contain memory addresses tend to be twice the size of the CPU's data size. Thus, the IP on an 8-bit CPU was 16-bits, and the IP on a 16-bit CPU was 32-bits.

Instruction Set

The instruction set of a given CPU model defines the basic operations that can be performed by the CPU. These operations tend to be simple, such as adding two numbers, outputting a character, or moving data between registers. In a given line of processors, the instruction sets are compatible, although as the newer models are released, they usually had additional instructions added. Thus, newer processors were backwards compatible (meaning they could run the same programs as older processors), but older processors did not recognize the new instructions added to later models. Between processor lines, there is no compatibility. The instructions are stored in memory as "machine code" which are bit patterns that represent certain instructions. These bit patterns represent entirely different operations on different processor lines, which means that a program written for one CPU will not run on a different CPU line.

There are two aspects to an instruction set.

  • Orthogonality: An instruction set is considered "orthogonal" if the instructions work with all general-purpose registers. Instruction sets which limit certain instructions to certain registers are not considered orthogonal. In reality, instruction sets fall somewhere along a spectrum between complete orthogonality and non-orthogonality. The PDP-11 has an example of an orthogonal instruction set.
  • RISC/CISC: Reduced Instruction Set Computers (RISC) have fewer instructions than Complex Instruction Set Computers (CISC), which requires more instructions to complete the same task than on CISC processors. The advantage to RISC instruction sets is that they can be implemented with fewer transistors, which allows faster instruction execution in theory. In practice, the clock rate is the same on RISC and CISC CPUs. However, more cores can be fit into a given semiconductor space with a RISC architecture. ARM processors are examples of RISC CPUs. Intel iAPX processors are examples of CISC CPUs.

See also

References

  1. ↑ Fetch-Decode-Execute Cycle

External links

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