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The basic operation of a CPU is the "Fetch, Decode, Execute" cycle.<ref>[http://www.it.jcu.edu.au/Subjects/cp1300/resources/lectnotes/system/fde.html Fetch-Decode-Execute Cycle]</ref> The ''instruction fetcher'' fetches instructions from memory. The ''control logic'' decodes and executes the instruction. The [[ALU ]] is used to perform arithmetic and logical operations such as adding a value in memory to a value in a register and storing the result in another register. On some CPUs, some instructions may require additional fetches from memory (e.g., to get or store operands). A program in memory is executed sequentially, with each instruction stored in a different memory location. The instruction pointer (IP) register keeps tracks of the current program position, and is updated (usually incremented) after each instruction is executed. == Architecture ==A CPU cycle's architecture distinguishes it from other CPUs. There are many aspects of CPU architecture. ===Data size===CPUs are defined by the number of bits that can be handled in a single operation. For instance, a 16-bit CPU handles 2 bytes of data with most of its operations. The amount of data that can be transferred to and from memory is this number of bits, which determines the width of memory required for a given CPU. Most CPUs on the market today are 64-bit CPUs. Operations can be performed on larger or smaller numbers of bits, but such operations tend to run more slowly because the CPU is optimized for it's native data size. ===Registers===Register sets are essentially a small amount of memory within the CPU, divided into a discrete number of registers. There are general-purpose registers that can be used by programs and special-purpose registers that are restricted to certain functions. General purpose registers are the native data size of the CPU. Thus a 32-bit CPU will have 32-bit wide general-purpose registers. Special-purpose registers are used to store flags indicating the result of arithmetic or logical operations, index into memory, and so forth. Typical registers used for indexing into memory were the Instruction Pointer (IP) - sometimes called the Program Counter (PC) - and the Stack Pointer (SP). Such registers which contain memory addresses tend to be twice the size of the CPU's data size. Thus, the IP on an 8-bit CPU was 16-bits, and the IP on a 16-bit CPU was 32-bits. ===Instruction Set===The instruction set of a given CPU model defines the basic operations that can be performed by the CPU. These operations tend to be simple, such as adding two numbers, outputting a character, or moving data between registers. In a given line of processors, the instruction sets are compatible, although as the newer models are released, they usually had additional instructions added. Thus, newer processors were backwards compatible (meaning they could run the same programs as older processors), but older processors did not recognize the new instructions added to later models. Between processor lines, there is no compatibility. The instructions are stored in memory as "machine code" which are bit patterns that represent certain instructions. These bit patterns represent entirely different operations on different processor lines, which means that a program written for one CPU will not run on a different CPU line. There are two aspects to an instruction set.* Orthogonality: An instruction set is considered "orthogonal" if the instructions work with all general-purpose registers. Instruction sets which limit certain instructions to certain registers are not considered orthogonal. In reality, instruction sets fall somewhere along a spectrum between complete orthogonality and non-orthogonality. The [[PDP-11]] has an example of an orthogonal instruction set.* RISC/CISC: Reduced Instruction Set Computers (RISC) have fewer instructions than Complex Instruction Set Computers (CISC), which requires more instructions to complete the same task than on CISC processors. The advantage to RISC instruction sets is that they can be implemented with fewer transistors, which allows faster instruction execution in theory. In practice, the clock rate is the same on RISC and CISC CPUs. However, more cores can be fit into a given semiconductor space with a RISC architecture. ARM processors are examples of RISC CPUs. Intel iAPX processors are examples of CISC CPUs. ==See also==* [[Moore's Law]]* [[IBM]], [[HP]], [[Dell]] and [[Microsoft]] [[Windows]]* [[Mobile device]]s: [[Smartphone]]s and [[tablet computer|tablets]]

<references/>{{reflist|2}}  == External links ==

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